This invention is related to computer systems and particularly depicts a method for deadlock avoidance among a plurality of clusters of symmetric multiprocessors (SMPs).
Today""s e-business environment places great demands on the computer systems that drive their infrastructure. This is especially true in the areas of system performance and availability due in large part to the increasing amount of data sharing and transaction processing inherent in large system applications. Another aspect of the e-business infrastructure is the unpredictability of the workloads which mandate the underlying computer systems to be highly scaleable. However, the importance of additional performance and scalability must always be tempered by the cost of the systems.
Historically system architects have used various means to achieve high performance in large tightly coupled symmetrical multiprocessor (SMP) computer systems. They range from coupling individual processors or processor clusters via a single shared system bus, to coupling processors together in a cluster, whereby the clusters communicate using a cluster-to-cluster interface, to a centrally interconnected network where parallel systems built around a large number (i.e. 32 to 1024) of processors are interconnected via a central switch (i.e. a crossbar switch).
The shared bus method usually provides the most cost efficient system design since a single bus protocol can service multiple types of resources. Furthermore, additional processors, clusters or peripheral devices can be attached economically to the bus to grow the system. However, in large systems the congestion on the system bus coupled with the arbitration overhead tends to degrade overall system performance and yield low SMP efficiency. These problems can be formidable for symmetric multiprocessor systems employing numerous processors, especially if they are running at frequencies that are two to four times faster than the supporting memory subsystem.
The centrally interconnected system usually offers the advantage of equal latency to shared resources for all processors in the system. In an ideal system, equal latency allows multiple applications, or parallel threads within an application, to be distributed among the available processors without any foreknowledge of the system structure or memory hierarchy. These types of systems are generally implemented using one or more large crossbar switches to route data between the processors and memory. The underlying design often translates into large pin packaging requirements and the need for expensive component packaging. In addition, it can be difficult to implement an effective shared cache structure.
The tightly coupled clustering method serves as the compromise solution. In this application, the term cluster refers to a collection of processors sharing a single main memory, and whereby any processor in the system can access any portion of the main memory, regardless of its affinity to a particular cluster. Unlike Non-Uniform Memory Access (NUMA) architectures, the clusters referred to in our examples utilize dedicated hardware to maintain data coherency between the memory and the hierarchical caches located within each cluster, thus presenting a unified single image to the software, void of any memory hierarchy or physical partitions such as memory bank interleaves. One advantage of these systems is that the tightly coupled nature of the processors within a cluster provides excellent performance when the data remains in close proximity to the processors that need it such as the case when data resides in a cluster""s shared cache or the memory bank interleaves attached to that cluster. In addition, it usually leads to more cost-efficient packaging when compared to the large N-way crossbar switches found in the central interconnection systems. However, the clustering method can lead to poor performance if processors frequently require data from other clusters, and the ensuing latency is significant, or the bandwidth is inadequate.
The other important aspect of today""s large systems is reliability and availability which is paramount in a web-based e-business. Thus, it""s not uncommon for such systems to incorporate mechanisms to transfer workloads from a failing processor to another processor, take failing memory off line, and balance workloads among the clusters to ensure the systems are available 24 hours per day 7 days per week. However, in a multi-node system structure, the potential exists for multiple processors or I/O devices to simultaneously request the same block of data to be transferred between the clusters, which can lead to situations where resources on different clusters deadlock against each other, thereby hanging the system.
The use of clusters of microprocessors is a rapidly growing approach to providing unprecedented overall system performance. However, in symmetric multiprocessing (SMP) computer systems, where each processor has equal access to a single shared main memory, many techniques are used to improve system performance by reducing or hiding memory access latencies or maintaining a high degree of concurrent operations. Many times, these techniques create conditions which can result in a cross-cluster deadlock. Because this area is still relatively immature with respect to other areas of computer hardware design, most of the prior art fails to comparably address the same aspects taught by the present invention.
U.S. Pat. No. 6,073,182 entitled Method of Resolving Deadlocks Between Competing Requests in a Multiprocessor Using Global Hang Pulse Logic describes a method of deadlock avoidance using a single technique known as Fast Hang Quiesce. The method taught by the invention primarily targets the processor and I/O controllers within a single cluster (or node) of a the System Controller (SC) described in the preferred embodiment of the present invention. Our invention teaches several improvements regarding deadlock avoidance employing a plurality of techniques, one of which contemplates the embodiment of the art within our invention to expand its capability to cover cross-cluster deadlocks.
U.S. Pat. No. 5,224,100, entitled Routing Technique for a Hierarchical Interprocessor-Communication Network Between Massively-Parallel Processors, describes a routing technique for a massively parallel single instruction-multiple data (SIMD) multilevel hierarchical nodes arranged in clusters. Although this invention teaches a method of deadlock avoidance, it is achieved within a special purpose apparatus designed to perform the single task of transferring data packets from a source processor to a receiving processor. On the other hand, the present invention provides a means of deadlock avoidance in a complex SMP computer system which entails performing many type of operations such as concurrent data accesses from main memory, shared caches, I/O devices, etc. as well as memory storage accesses and cache coherency operations.
U.S. Pat. No. 4,754,398, entitled System for Multiprocessor Communication Using Local and Common Semaphore and Information Registers also teaches a method of deadlock detection, but it is limited to a single operation analogous to an I/O Test and Set operation in the present invention. The method described herein is achieved through the use of dedicated signaling among all the processors in the system. Such an implementation is not practical in the present invention since it employs a large system with 16 or more processors arranged in packages that preclude dedicated signaling between all of them. Furthermore, our invention employs deadlock methods to cover all types of fetch and store operations from processors and I/O devices.
The present invention describes various methods designed to avoid cross-cluster deadlocks. By utilizing a combination of design advances, including an optimized cache coherency scheme and the principles described in U.S. Pat. No. 6,038,651 entitled SMP Clusters with Remote Resource Management for Distributing Work to Other Clusters while Reducing Bus Traffic to a Minimum, our invention teaches various methods to proactively avoid deadlock situations as opposed to detecting the deadlock and employing some type of recovery scheme. These deadlocks become more frequent as the size and complexity of large systems increases, and often they require restarting the system, thereby decreasing productivity and/or availability.
The preferred embodiment is incorporated into an Symmetric Multiprocessing System comprising a plurality of Central Processors, each having a private L1 cache, a plurality of I/O Adapters, and a main memory wherein any Processor or I/O Adapter can access any portion of the memory. The total number of Processors and I/O Adapters are divided equally into two clusters. In addition, the main memory is comprised of banks or interleaves, half of which are attached to each cluster.
Within each cluster there exists a System Controller which consists of a system coherency management unit, cluster shared cache, various controllers, and discrete interfaces (or ports) to every Processor, I/O Adapter, and the main memory. The cache represented in the present embodiment is comprised of a plurality of banks or interleaves and the contents are managed by a 16-way associative directory. The System Controller depicted in FIG. 1 illustrates the major functional elements and will be described further in the detailed description of the preferred embodiment. However, a brief overview of the System Controller within a single cluster is beneficial in understanding the aspects of the present invention.
The primary function of the System Controller is to process data fetch and store requests coherently between the Processors and I/O Adapters and the system""s main memory. Since the System Controller contains a shared cache, which is architecturally invisible to the software and operating system, the System Controller is also responsible for performing directory and cache accesses. All incoming requests enter a port on the System Controller, where they are received by a Central Processor (CFAR) or I/O Controller. These controllers generate requests into a Central Priority unit which arbitrates among them and chooses one of the requesters to enter into one of two multistage Pipelines based on the address. During each stage of the pipeline the requester accesses and/or reserves various resources such as the cache, the Local Cache Fetch/Store Controllers, the data path controls, data path FIFO buffers, the Remote Fetch/Store Controllers, etc.
Directory accesses are made to determine the state of the requested block of data. Requests exiting the pipeline that miss the local cache become the responsibility of one of the Local Fetch/Store Controllers. These controllers manage the subsequent fetch and store operations that must be dispatched to the remote nodes and/or main memory. Often this requires additional passes through the pipeline, therefore a Local Fetch/Store Controller must also participate in Central Priority arbitration, and is also considered a requester. In the present embodiment, we include the Cache Controller and the Main Memory Controller, as part of the Local Fetch/Store Controllers, Between them they contain all the resources (including data path elements such as FIFO buffers and cross point switches) necessary to access data from the cache interleaves, process data accesses to main memory when cache misses occur, perform store operations into the cache interleaves, and cast out aged data (using a Least Recently Used method) from the cache into main memory in order to make room for incoming data from main memory accesses.
As stated above, the main memory banks are physically distributed between the two clusters of the BI-nodal system. However, the main memory appears as a single unified entity to any of the Processors or I/O Adapters located anywhere in the SMP system. Therefore, the present embodiment incorporates an additional set of controllers, known as Remote Fetch/Store Controllers. The System Controller keeps track of which main memory addresses are assigned to the memory banks on each cluster. Whenever data accesses (fetch requests) miss the cache on the local cluster, (where the term local refers to the cluster to which the originating Processor or I/O Adapter is attached), the Local Fetch/Store Controller must interrogate the remote (or xe2x80x9cotherxe2x80x9d) cluster to see if the data resides in that cache. These remote interrogations are processed by the Remote Fetch Controllers, which make requests into Central Priority and access resources in a similar fashion to the Local Fetch/Store Controllers.
In addition, if the data access misses the remote cache, but the address denotes that it belongs to a memory bank attached to the remote cluster, the Remote Fetch/Store Controller also interacts with the Main Memory Controller to initiate main memory accesses. For operations which necessitate storing data into memory (such as casting aged data out of the cache), the address once again determines whether the Local Fetch/Store Controller can process the entire operation or if a remote store operation must be initiated across the BI-nodal interface. In this situation, the remote store operations are processed by the Remote Store Controller who also interacts with the Main Memory Controller to store the data into the memory interleaves. As with the Local Fetch/Store Controllers, their remote counterparts also contain all the resources (including data paths, FIFO buffers, and cross point switches) necessary to process inter-cluster operations.
The present invention also interacts with a remote management system for managing the resources comprising the aforementioned Remote Fetch/Store Controllers, and to distribute work to these Remote Fetch/Store Controllers, who in turn, act as agents to perform the desired operation without requiring knowledge of the requester who initiated the work request. Work is distributed only when a remote resource is available for processing the work, without a need for constant communication between multiple clusters of symmetric multiprocessors. These operations are initiated via a command interface and completion or error conditions are reported back on a response bus. Also in the preferred embodiment, the Local and Remote Fetch Controllers rely on a special synchronous XI response bus to indicate whether data hits or misses in the remote cache on a fixed number of cycles after the command is sent across the interface.
The present invention focuses on cross cluster deadlock avoidance while maintaining system level data coherency and a high level of system performance. The techniques described herein enable a multitude of operations to occur in a concurrent and high speed manner using a minimal number of external control signals.
In a non blocking switch design, such as the IBM eServer Z-Series, where multiple concurrent operations are allowed for improved system throughput, special care must be taken to maintain data coherency. Data integrity is compromised when operations to the same storage data are allowed to overrun, resulting in misplacement of true data and also bad ownership assignments. Prior generations of S/390 Enterprise Server designs have avoided this problem by employing a series of varied address comparators that are observed by each operation as it processes through the centralized multistage pipeline. Specifically, these address compares protect against concurrent conflicting data access by multiple requesters. They also protect data in transit between clusters and between cache and main memory.
In Bi-Nodal SMP designs, such as the S/390 enterprise server generation 5 design, some of the requesters are attached to one node and begin processing on this node while the remaining requesters are attached to the other node. When a request from one node requires an operation to be sent to the other node (such as a Main Storage data fetch or store), the operation is loaded into a Remote Fetch (a.k.a. RFAR) or Remote Store (a.k.a. RSAR) resource on the other node. This operation may conflict with an operation started by a requester local to the same node. Therefore a special set of address comparators involving these RFAR and RSAR resources needs to be implemented to prevent concurrent operation of a Remote operation with a Local operation.
These set of address comparators may result in the creation of system deadlock scenarios where multiple operations are all stuck waiting for each other to complete. Contributing to this problem is a local operation in one node may require a corresponding remote operation in the other node to complete before it is able to complete. For example, a local operation on cluster A could be stuck waiting for a remote operation in cluster B to complete an operation on it""s behalf, but the remote operation in cluster B is stuck waiting for a local operation in cluster B to complete due to an address compare interlock. The cluster B local operation could be stuck waiting for a cluster A remote operation to complete on it""s behalf, but the cluster A remote operation is stuck waiting for the cluster A local operation to complete due to an address compare interlock. The result is a deadlock where neither of the local operations can complete, eventually resulting in a system hang.
This disclosure identifies techniques implemented to avoid specific cross-nodal deadlock cases caused by the existence of these address compare interlocks while still maintaining the required data consistency.
The present invention employs a combination of address compare interlocks and cache management methods to detect potential cross-cluster deadlocks and circumvent them, while maintaining data integrity across a plurality of processor clusters. As previously described, a deadlock occurs when a resource is stuck waiting for another resource, which is waiting for another resource, and so on. Typically these resources can""t progress through their operational sequences because they""ve encountered an address compare interlock against another resource. One would surmise that the easiest way to circumvent deadlocks is to simply ignore these interlocks and allow the operation to proceed.
However, these interlocks are required to maintain coherency. The following examples illustrate our method for safely ignoring interlocks while still maintaining proper data integrity.
In order to understand the following examples, one must first understand that the preferred embodiment resides in a computer processing system comprised of a plurality of clusters, wherein each cluster contains connections to a multitude of processors, connections to a multitude of I/O processors, connections to a shared main memory, a shared cache, one or more centralized pipelines for serializing storage and resource accesses, and an interface between the clusters known as the Remote Storage Cluster (RSC) interface. Also contained within a storage cluster is a plurality of requesters with the following functions:
LFAR: Used to manage fetch requests to main memory on the local cluster and initiate fetch requests to the remote cluster
LSAR: Used to manage store requests to main memory on the local cluster and initiate store requests to the remote cluster
RFAR: Used to manage fetch requests initiated by a corresponding LFAR from the other cluster. RFAR performs the fetch operation on behalf of the remote LFAR and returns the data to said LFAR across the RSC interface.
RSAR: Used to manage store requests initiated by a corresponding LSAR from the other cluster. RSAR performs the store operation on behalf of the remote LSAR and accepts the data from said LSAR across the RSC interface.
Note: In addition to data fetches and stores, all of these resources also perform various directory update operations.
A explanation of the following operations may be beneficial in understanding the mechanics behind the present invention""s deadlock avoidance methods. The LFAR, LSAR, RFAR and RSAR controllers typically process:
Data Fetches from main memory or a cache.
Directory Invalidations which invalidate the block of storage in the cache and can be
the Read-Only type (RO INV) that broadcasts to the central processor to invalidate their read-only copies of the block of data. These are typically the result of a processor requesting exclusive ownership of the block of data.
the Exclusive type (EX INV) that broadcasts to the central processor to relinquish ownership of their copy of the data and write any modifications to the data back into the cache
LRU Cast Outs to store xe2x80x9cagedxe2x80x9d modified cache data into main memory
Store Physical Absolute to store data sent from a central processor directly into a main memory location, bypassing the cache hierarchy
Store Pad to replicate a data pattern dictated by a central processor into a main memory location.
Move Page Operations which consist of a Fetch and Store designed to relocate a page of storage from a source main memory (fetch) address to a target main memory (store) address
I/O Store to store 128 or 256 bytes of I/O data into a main memory location or directly into the shared L2 cache if the data is already resident in the cache.
The present invention classifies system operations into three types of potential deadlocks, and employs a different method for avoiding each type. In all three cases, it is presumed that the requesters are vying for the same block of data, thus triggering an address compare situation. In addition, our invention also incorporates a fourth method of deadlock avoidance known as Fast Hang Quiesce which is not based on address compares, and is designed to recover from any hang situations which could result from either unresolved deadlocks or hardware failures.
RFAR vs. RFAR:
These situations involve an LFAR on each cluster sending either a data fetch request or read-only directory invalidation to the corresponding RFAR on the other side. In addition, both operations are vying for data belonging to the same line. The potential for a deadlock exists because the LFAR on cluster A is waiting for its corresponding RFAR on cluster B. The RFAR on cluster B encounters a compare against the LFAR on cluster B, who is waiting for its RFAR on cluster A. The RFAR on cluster A sees a compare against the LFAR on cluster A. Thus, neither of the four resources can progress. In this case, our invention employs an address-based mechanism which indicates whether the request is targeting main memory (PMA) on a local or remote node. This bit, also known as the local PMA bit, ultimately determines which of the remote fetches will be permitted to continue.
The aforementioned scenario assumes complete overlap of the two fetch requests. One can appreciate how these requests can be skewed in such a way that data is already being transferred, or a main memory request has already been issued, before the second request is loaded into the RFAR. Our invention contemplates this situation and employs a signaling technique between the LFARs and RFARs on the same cluster to indicate when a data return is eminent. If an RFAR compares against an LFAR whose data return is eminent, it must honor its compare, regardless of the local PMA bit.
Another aspect of our invention is revealed when one or more of the RFARs on each node are processing a read-only directory invalidation. The operation results from a processor on the remote node requesting the data exclusively, with the data potentially existing read-only in both caches. The end result of this operation is for read-only XIs to be broadcast to all the CPs on the remote side, the remote cache to be invalidated, and the processor on the local side to own the data exclusively. In order to ensure the cache coherency is maintained, the RFAR which has to honor its compare always completes the operation by returning a reject response to the other side. This ensures the LFAR on the other side will return the request to be recycled through the central pipeline, thereby ensuring the initial requester will see the correct directory state.
RFAR vs. RSAR
These situations involve an LFAR on one cluster sending either a data fetch request or read-only directory invalidation to the corresponding RFAR on the other side. Meanwhile an LSAR on the other cluster initiates an operation to its corresponding RSAR on the first cluster. In addition, both operations are vying for data belonging to the same line. The potential for a deadlock exists because the LFAR on cluster A is waiting for its corresponding RFAR on cluster B. The RFAR on cluster B encounters a compare against the LSAR on cluster B, who is waiting for its RSAR on cluster A. The RSAR on cluster A sees a compare against the LFAR on cluster A. Thus, none of the four requesters can progress. In the general case, our invention requires an RFAR that encounters a compare against an LSAR to honor the compare and wait for the LSAR to complete. Additionally, the RSAR on the other side will ignore its compare against the LFAR and complete the operation. Upon returning its response to the corresponding LSAR on the other side, the RFAR on the other side will be able to proceed with its operation. Unlike the RFAR vs. RFAR scenarios, the RFAR in this situation can encounter a directory miss during a subsequent pipe pass after detecting the LSAR compare. This can occur due to the LSAR performing a directory invalidation as part of an operation such as a Store Pad or LRU Cast Out. Normally, if the LSAR operation targets the remote side, the RFAR will terminate by sending back a xe2x80x9cmissxe2x80x9d final response.
Just as in the previous category, the same exception applies concerning returning data. The LSARs and RSARs within a cluster employ the same signaling technique previously described to indicate when a data return is eminent. If an RSAR encounters a compare and a data return is eminent, it must honor the compare and wait for the LFAR to complete. Also, just as described in the previous category, if the RFAR is processing a read-only invalidate, it will return a reject response to force the initial requester to recycle the request.
RSAR vs. RSAR
These situations involve an LSAR on each cluster initiating an operation to the corresponding RSAR on the other side. In addition, both operations are vying for data belonging to the same line. The potential for a deadlock exists because the LSAR on cluster A is waiting for its corresponding RSAR on cluster B. The RSAR on cluster B encounters a compare against the LSAR on cluster B, who is waiting for its RSAR on cluster A. The RSAR on cluster A sees a compare against the LSAR on cluster A. Thus, none of the four resources can progress. Due to the number of different operations the RSAR in the preferred embodiment can process, the method used to avoid the deadlock is command dependent.
To begin with, the preferred embodiment contemplates the use of a cache management scheme which guarantees that remote LRU cast outs will always miss the remote cache. Therefore, to improve performance, RSAR processes LRU cast outs in an asynchronous fashion and bypasses the centralized pipeline. Since these LRU operations don""t require RSAR to perform any cache coherency tasks, our invention allows any RSAR processing them commands to automatically ignore any interlocks it encounters.
Secondly, an RSAR in the present invention will ignore a compare against an LSAR if the LSAR is processing an I/O Store or I/O Query operation targeting that cluster. This is permitted because architecturally I/O Stores are not guaranteed in any specific order or relationship to other operations in the system. For example, if RSAR is processing a Store Pad, it is allowed to proceed with the main memory store operation while the local LSAR is also processing an I/O Store. Cache coherency is maintained in the following manner. For a compare to occur, the RSAR operation must be targeting the same cluster as the I/O Store. Furthermore, LSAR is only loaded with an I/O Store if it misses the local cache. In order to maintain coherency, the local LSAR must query the remote cache to see if the line exists there. If the query is sent after the remote side has initiated the RSAR operation, the query will encounter a compare against the LSAR on the other cluster and wait. This ensures the RSAR operation on the local cluster completes first and performs all necessary directory updates prior to allowing the I/O Store to continue. On the other hand, if the query completes before the RSAR operation initiates, or if the query indicates a miss in the remote cache, then the I/O Store proceeds out to the local main memory and an architecturally permissible race condition ensues.
In addition to the aforementioned case, RSAR can also safely ignore compares when the local LSAR is processing a Store Pad or Move Page Storage op and RSAR is processing any operation. Furthermore, if RSAR is processing something other than a remote LRU cast out, our invention employs an additional performance enhancement by actually aborting the operation. Thus, rather than spend time transferring data to main memory or making directory update pipe passes, RSAR simply returns a completion response as if the operation occurred. This results in significant performance improvements in systems comprising extensive memory latency or constricted memory bandwidth in comparison to processor performance. Once again, this is permissible since S/390 system architecture allows Store Pads and Move Page Store operations to be processed without order.
The final case dictates the conditions requiring RSAR to honor any compare it encounters. These cases occur when the local LSAR is processing an LRU cast out and RSAR is processing any operation other than a remote LRU cast out. Since the LSAR is processing a cast out, it must either target the local or remote side. If it targets the local side, a deadlock is not possible because the RSAR will simply honor the compare and wait for the cast out to complete. On the other hand, if the LSAR cast out targets the remote side, it will load the RSAR on the other side. However, our invention avoids any potential deadlock by allowing the remote cast out to complete asynchronously, thereby bypassing any interlocks.
Generation of Rejects Responses by RFAR or RSAR
The present invention further improves upon prior art by enlisting a form of active and passive hang detection within the Remote Fetch and Store Controllers. The RFAR and RSAR controllers work in a passive manner to achieve deadlock avoidance by forcing a reject response when the existence of a fast hang quiesce (fhq) condition emanating from elsewhere in the SC has been detected. Additionally, the present invention also permits the RFAR and RSAR controllers to actively participate in the generation of a fast hang quiesce condition to be broadcast to other controllers in the SC. This is achieved through the use of a Global Hang Counter in the SC which generates the fhq pulses that are used to monitor progress through the SC. Each SC controller (including RFAR and RSAR) activates its own internal hang pulse when the number of fhq pulses it receives reaches a predetermined count known as the internal hang limit. If two consecutive internal hang pulses are generated, it""s indicative of a potential hang condition. The controller responds by activating its fhq request latch which results in the broadcast of the fhq condition to all SC controllers. The newly activated fhq condition results in all subsequent requests being forced temporarily inactive (i.e. quiesced) in order to allow all currently active operations to complete. If RFAR or RSAR detects the fhq active condition during a valid operation, then that RFAR or RSAR operation will be rejected. This improves the probability of completing all currently active SC operations since the RFAR or RSAR reject results in the removal of any possible interlock conditions than any other SC requester may have had with RFAR or RSAR.
Although the internal functionality of the central SC Fast Hang Quiesce mechanism is largely unchanged from that cited in the Prior Art as U.S. Pat. No. 6,073,182, the present invention expands the use of this mechanism to include the remote facilities. In doing so, some care must be exercised to ensure that the RFAR/RSAR reject due to fhq mechanism itself does not result in any hardware loop or deadlock conditions. For this reason, activation of this mechanism is dynamically blocked if any of the following conditions are true;
1. The RFAR or RSAR is already in the process of generating a response.
2. A reject response for this RFAR or RSAR has already been issued during this quiesce period.
3. The RFAR or RSAR is in one of the following states:
a. The internal state machine is not in the initial state
b. The internal state machine is in the initial state, it hasn""t encountered any compare and it""s not currently waiting for any resources.
In addition, the following mode and disable switches are implemented for maximum flexibility:
1. Reject current op: Results in reject response for current RFAR or RSAR op assuming none of the blocking conditions described above are active.
2. Reject next fetch: Results in reject response for next RFAR op (instead of current RFAR op) assuming none of the blocking conditions described above are active.
3. Disable reject due to self: Blocks forcing of reject response if this RFAR or RSAR initiates fhq request.
4. Disable reject due to others: Blocks forcing of reject response if a requester other than this RFAR or RSAR initiated the fhq request.
The present invention improves upon prior implementations of S/390 Enterprise Servers in several aspects. To begin with, the S/390 G5 and G6 Enterprise Servers contain more Local Fetch/Store Address Registers (LFAR/LSAR) than Remote Fetch/Store Address Registers (RFAR/RSAR). In addition, the RFAR/RSARs are floating and can service any LFAR/LSAR on the remote cluster. This imbalance increases the likelihood of a cross-cluster deadlock due to the inability of the RFAR/RSAR resources to service all the LFAR/LSARs simultaneously. Our invention utilizes an equal number of LFAR/RFAR and LSAR/RSAR pairs, and also incorporates a fixed affinity between each LFAR/RFAR and LSAR/RSAR. This ensures that
each LFAR/LSAR operation in need of a remote resource, will be guaranteed to have one available, thus reducing the chances of encountering deadlocks while improving performance.
Another innovation of our invention is the use of an I/O Query followed by an remote I/O Store, if necessary. Previous binodal systems required all I/O Stores to be performed to the local side. Therefore, a special remote force cast out command was issued to the remote cluster to test if the line existed in that cache. If so, the RSAR on the remote side would enlist an LSAR on the remote side to perform a cast out of the data back to the local side. The entire operation utilized four resources:
the local LSAR initiating the force cast out
the remote RSAR servicing the force cast out
the remote LSAR which the remote RSAR enlisted to perform the cast out
the local RSAR which received and processed the force cast out data
The present invention always only utilizes a single LSAR/RSAR pair to perform any remote operation, further eliminating the potential for cross-cluster deadlocks.
A further improvement over prior S/390 systems is the use of an abort mechanism within RSAR to detect when an RSAR operation can be architecturally thrown away. This feature not only aids in deadlock avoidance, but improves performance as well since costly memory accesses are spared.
In comparison to non-S/390 systems, one common approach in other systems is to reject operations back to the requester if resource or address conflicts arise. In addition to degrading overall system performance this approach often incites additional cross interrogation or xe2x80x9cbus snoopingxe2x80x9d traffic. The present invention minimizes rejections to only those cases where the line has changed global state in the cache.
Lastly, our invention employs a fast hang quiesce mechanism within both RFAR and RSAR to detect system hangs and reject their current operation. This differs from prior systems in two respects. First, systems such as the G5 and G6 relied on the other SC resources (CFAR, CSAR, MAR, LFAR, LSAR, etc.) to detect system hangs and recycle their operation, whereas our invention embeds the detection logic within the remote controllers. Second and most importantly, fast hang quiesce was the only means of deadlock prevention in prior systems, whereas our invention uses it as a last resort in the event a deadlock occurs. In other words, the present invention takes a proactive approach in an effort to avoid deadlocks altogether while prior art tends to focus on resolving the deadlock in a reactionary manner.
Although the present invention is being described in association with the present preferred embodiment, one skilled in the art will appreciate that the concepts disclosed herein are applicable to systems comprising more than two clusters, and utilizing Storage Clusters differing from our present embodiment. Additionally, the present invention contemplates alternate System Controller embodiments with a different number and configuration of functional units, including, but not limited to, the cache structure, the main memory organization, the number and size of data path resources (such as buffers, control busses, etc.), the composition of the various controllers, and the number and size of the Pipelines.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.